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74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs
October 1992 Revised April 2005
74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD
3.6ns (typ) at TA VNIL
25qC 25qC 28% VCC (min)
s Low power dissipation: ICC s High noise immunity: VNIH s Low noise: VOLP
4 PA (max) @ TA
s Power down protection is provided on all inputs
0.9V (max)
s Pin and function compatible with 74HC240
Ordering Code:
Order Number 74VHC240M 74VHC240SJ 74VHC240MTC 74VHC240N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
(c) 2005 Fairchild Semiconductor Corporation
DS011506
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74VHC240
Pin Descriptions
Pin Names OE1, OE2 I0-I7 O0-O7 Description 3-STATE Output Enable Inputs Inputs Outputs 3-STATE Outputs
Truth Tables
Inputs OE1 L L H Inputs OE1 L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Outputs In L H X (Pins 12, 14, 16, 18) H L Z Outputs In L H X (Pins 3, 5, 7, 9) H L Z
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74VHC240
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r 0.3V 5.0V r 0.5V 0 ns/V a 100 ns/V 0 ns/V a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC
40qC to 85qC
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 5.5 2.0 3.0 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 0 5.5 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VOUT VIN VIN VIH or VIL VCC or GND 5.5V or GND VCC or GND 4 mA 8 mA V V VIN IOH IOH VIH IOL or VIL TA 25qC Typ Max TA
40qC to 85qC
Max
Min 1.50 0.7 VCC
Units V
Conditions
0.50 0.3 VCC
V V VIN VIH IOH or VIL
50 PA
4 mA 8 mA
50 PA
r0.25 r0.1
4.0
r2.5 r1.0
40.0
PA PA PA
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA Typ 0.6 25qC Limits 0.9 Units V V V V CL CL CL CL Conditions 50 pF 50 pF 50 pF 50 pF
0.6
0.9
3.5 1.5
Note 3: Parameter guaranteed by design.
3
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74VHC240
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time 5.0 r 0.5 tPZL tPZH 3-STATE Output Enable Time tPLZ tPHZ tOSLH tOSHL CIN COUT CPD 3-STATE Output Disable Time Output to Output Skew Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design. tOSLH |tPLHmax tPLHmin|; tOSHL |tPHLmax tPHLmin| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) C PD * VCC * fIN ICC/8 (per bit).
VCC (V) 3.3 r 0.3 Min
TA
25qC Typ 5.3 7.8 3.6 5.1 6.6 9.1 4.7 6.2 10.3 Max 7.5 11.0 5.5 7.5 10.6 14.1 7.3 9.3 14.0 9.2 1.5 1.0 4 6 17 10
TA
40qC to 85qC
Max 9.0 12.5 6.5 8.5 12.5 16.0 8.5 10.5 16.0 10.5 1.5 1.0 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Min
Units ns ns ns RL ns ns ns pF pF pF RL
Conditions CL CL CL CL CL 1 k: CL CL CL 1 k: CL CL CL CL 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 50 pF 50 pF 50 pF 50 pF
3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 6.7
(Note 4) VCC VCC Open 5.0V
(Note 5)
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74VHC240
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74VHC240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74VHC240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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